Raising Your Chip Design AI

You cannot trust third-party models with sensitive IP. SiliconMind builds your chip design AI that evolves on-premise with your data.

Why SiliconMind

SiliconMind is a Taiwan-based Chip AI Foundry, spun off from National Taiwan University and Academia Sinica. Custom ASIC demand is outpacing the industry's ability to hire RTL design & verification talent, and turnkey services still run on human labor. We build private AI for IC design companies and IP providers — small, efficient models served on-premise, continuously improving on the customer's own design data and workflows. The AI belongs to the customer, and their design knowledge never leaves their environment. Like a semiconductor foundry, we provide the infrastructure to scale without competing with our customers. Current scope: spec to verified RTL, on a roadmap to spec to GDSII.

The foundry model

01

Capture

Ingest approved engineering sources (text, data, visual artifacts) using our secure local collecting tool into a traceable knowledge substrate.

  • Specifications, architecture notes, and issue trails
  • Waveforms, layout snapshots, and schematic captures (Vision)
02

Curate

Normalize, filter, and segment domain context so retrieval (RAG) and evaluation stay reliable.

  • Task-oriented corpus design
  • Access controls and refresh cycles
03

Learn

Continuous local model training service (LLM and Multi-modal) based on captured context and human feedback.

  • IC-aware domain adaptation
  • Model routing by task profile
  • Human review checkpoints
04

Verify

Measure outputs against engineering expectations before they influence critical decisions.

  • Evaluation suites and audits
  • Decision lineage for downstream teams
05

Evolve

Leverage test-time scaling and search-based reasoning to autonomously optimize design candidates for peak evaluation.

  • Test-time compute scaling for deep design-space exploration
  • Iterative RTL mutation targeting PPA (Power, Performance, Area) optimization

The tech stack

RAG + Vision

Engineering context ingestion

Connect the artifacts and repositories that actually drive design decisions, fully on-prem.

  • Structured document pipelines
  • Visual schematic and waveform understanding
  • Traceable RAG architecture
LLM Learning

Task-shaped model adaptation

Continuous local learning service routes prompts and tools through IC-aware patterns.

  • Workflow-specific prompt systems
  • On-premise continuous training
  • IC design-lineage control
Verification

Validation and optimization

Support analysis, synthesis, and inspection steps that sit close to engineering delivery.

  • Spec and review summarization
  • Verification knowledge access
  • Approval-aware assistant outputs
  • Test-time scaling for design-space exploration

Our People

Officers and Advisors

Mu-Chi Chen portrait

Mu-Chi Chen

陳牧祈

Co-Founder & CEO

Cheng Liang portrait

Cheng Liang

梁正

COO

H.-T. Kung portrait

H.-T. Kung

孔祥重

Co-Founder & Advisor

William H. Gates Professor of Computer Science at Harvard University

Shih-Hao Hung portrait

Shih-Hao Hung

洪士灝

Co-Founder

Professor of Computer Science and Information Engineering at National Taiwan University

Keng-Tai Ko portrait

Keng-Tai Ko

柯亘泰

Advisor

Previously: Sr. Director, Enterprise Architecture, Fannie Mae; Director, Cloud Engineering, Capital One; Sr. Director, Performance and Application Engineering, Sun/Oracle

Jeng-Feng Lee portrait

Jeng-Feng Lee

李政鋒

Advisor

(former) Technical Director of New Business Development, Mediatek Inc.; (former) Chairman and COO of Origin Wireless Inc.; Founder and Chairman of Sensec, Inc.

Joseph Yeh portrait

Joseph Yeh

葉學禮

Advisor

Team

En-Ming Huang portrait

En-Ming Huang

Tech Lead

Po-Hsuan Huang portrait

Po-Hsuan Huang

Research Lead

Hsiang-Yu Tsou portrait

Hsiang-Yu Tsou

Engineering Lead

Yu-Te Ku portrait

Yu-Te Ku

AI Security

Journal

Technical Blog & Research Notes

Thoughts on secure AI deployment, continuous local learning, and the future of semiconductor knowledge systems.

Our latest thinking on building private AI systems for IC design and verification teams, from platform architecture to domain datasets to evaluation frameworks.

Partner with SiliconMind

Bring AI into Chip Design without Training Others’ Models

Email [email protected] to get in touch.